View ADG120409_6990329.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low capacitance, low charge injection, 15 v/+12 v, 4:1 i cmos multiplexer adg1204 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2009 analog devices, inc. all rights reserved. features 1.5 pf off source capacitance <1 pc charge injection 33 v supply range 120 on resistance fully specified at 15 v, +12 v no v l supply required 3 v logic-compatible inputs rail-to-rail operation 14-lead tssop and 12-lead lfcsp_vq typical power consumption < 0.03 w applications automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems audio signal routing video signal routing communication systems functional block diagram adg1204 s2 s1 d s4 s3 en a1 a0 1 of 4 decoder 04779-001 figure 1. general description the adg1204 is a complementary metal-oxide semiconductor (cmos) analog multiplexer, comprising four single channels designed on an i cmos (industrial cmos) process. i cmos? is a modular manufacturing process that combines high voltage cmos and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no previous generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. the ultralow capacitance and charge injection of this multiplexer makes it an ideal solution for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. fast switching speed coupled with high signal bandwidth makes the part suitable for video signal switching. i cmos construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. the adg1204 switches one of four inputs to a common output, d, as determined by the 3-bit binary address lines: a0, a1, and en. logic 0 on the en pin disables the device. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condi- tion, signal levels up to the supplies are blocked. all switches exhibit break-before-make switching action. product highlights 1. 1.5 pf off capacitance (15 v supply). 2. <1 pc charge injection. 3. 3 v logic-compatible digital inputs: v ih = 2.0 v, v il = 0.8 v. 4. no v l logic power supply required. 5. ultralow power dissipation: <0.03 w. 6. 14-lead tssop and 12-lead, 3 mm 3 mm lfcsp_vq packages.
adg1204 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? specifications ..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply ................................................................................. 5 ? absolute maximum ratings ............................................................ 7 ? esd caution...................................................................................7 ? pin configurations and function descriptions ............................8 ? truth table .....................................................................................8 ? typical performance characteristics ..............................................9 ? test circuits ..................................................................................... 12 ? terminology .................................................................................... 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 2/09rev. a to rev. b changes to power requirements, i dd , digital inputs = 5 v parameter, table 1 ............................................................................. 4 changes to power requirements, i dd , digital inputs = 5 v parameter, table 2 ............................................................................. 6 updated outline dimensions ....................................................... 15 7/06rev. 0 to rev. a updated format .................................................................. universal changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to the terminology section ........................................... 14 7/05revision 0: initial version
adg1204 rev. b | page 3 of 16 specifications dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. y version 1 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 120 typ v s = 10 v, i s = ?1 ma; see figure 21 190 230 260 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between 3.5 typ v s = 10 v, i s = ?1 ma channels (r on ) 6 10 12 max on resistance flatness (r flat(on) ) 20 typ v s = ?5 v, 0 v, +5 v; i s = ?1 ma 57 72 79 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.02 na typ v s = 10 v, v d = ? 10 v; see figure 22 0.1 0.6 1 na max drain off leakage, i d (off) 0.02 na typ v s = 10 v, v d = ? 10 v; see figure 22 0.1 0.6 1 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 10 v; see figure 23 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i nh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 2 transition time, t trans 120 ns typ r l = 300 , c l = 35 pf 150 180 200 ns max v s = 10 v; see figure 24 t on (en) 70 ns typ r l = 300 , c l = 35 pf 85 100 110 ns max v s = 10 v; see figure 26 t off (en) 90 ns typ r l = 300 , c l = 35 pf 110 135 155 ns max v s = 10 v; see figure 26 break-before-make time delay, t d 25 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 10 v; see figure 25 charge injection ?0.7 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 27 off isolation 85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 channel-to-channel crosstalk 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 30 total harmonic distortion + noise 0.15 % typ r l = 10 k, 5 v rms, f = 20 hz to 20 khz; see figure 31 bandwidth ?3 db 800 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s (off) 1.2 pf typ f = 1 mhz, v s = 0 v 1.5 pf max f = 1 mhz, v s = 0 v c d (off) 3.6 pf typ f = 1 mhz, v s = 0 v 4.2 pf max f = 1 mhz, v s = 0 v c d , c s (on) 5.5 pf typ f = 1 mhz, v s = 0 v 6.5 pf max f = 1 mhz, v s = 0 v
adg1204 rev. b | page 4 of 16 y version 1 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 170 a typ digital inputs = 5 v 285 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i ss 0.001 a typ digital inputs = 5 v 1.0 a max 1 y version temperature ra nge is ?40c to +125c. 2 guaranteed by design, not subject to production test.
adg1204 rev. b | page 5 of 16 single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. y version 1 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 300 typ v s = 0 v to 10 v, i s = ?1 ma; see figure 21 475 567 625 max v dd = 10.8 v, v ss = 0 v on resistance match between channels 5 typ v s = 0 v to 10 v, i s = ?1 ma (r on ) 16 26 27 max on resistance flatness (r flat(on) ) 60 typ v s = 3 v, 6 v, 9 v; i s = ?1 ma leakage currents v dd = 13.2 v source off leakage, i s (off) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; 0.1 0.6 1 na max see figure 22 drain off leakage, i d (off) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; 0.1 0.6 1 na max see figure 22 channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 1 v or 10 v; see figure 23 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 2 transition time, t trans 150 ns typ r l = 300 , c l = 35 pf 190 240 265 ns max v s = 8 v; see figure 24 t on (en) 95 ns typ r l = 300 , c l = 35 pf 120 150 170 ns max v s = 8 v; see figure 26 t off (en) 100 ns typ r l = 300 , c l = 35 pf 125 155 170 ns max v s = 8 v; see figure 26 break-before-make time delay, t d 50 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 8 v; see figure 25 charge injection ?0.4 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 27 off isolation 85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 channel-to-channel crosstalk 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 30 bandwidth ?3 db 550 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s (off) 1.2 pf typ f = 1 mhz; v s = 6 v 1.5 pf max f = 1 mhz; v s = 6 v c d (off) 3.6 pf typ f = 1 mhz; v s = 6 v 4.2 pf max f = 1 mhz; v s = 6 v c d , c s (on) 5.5 pf typ f = 1 mhz; v s = 6 v 6.5 pf max f = 1 mhz; v s = 6 v
adg1204 rev. b | page 6 of 16 y version 1 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 170 a typ digital inputs = 5 v 285 a max 1 y version temperature ra nge is ?40c to +125c. 2 guaranteed by design, not subject to production test.
adg1204 rev. b | page 7 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current 45 ma operating temperature range automotive (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 14-lead tssop, ja thermal impedance (4-layer board) 112c/w 12-lead lfcsp_vq, ja thermal impedance 80c/w reflow soldering peak temperature, pb free 260c 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adg1204 rev. b | page 8 of 16 pin configurations and function descriptions top view (not to scale) 1 2 3 4 5 en 6 7 nc = no connect v ss s1 s2 a0 nc d 14 13 12 11 10 gnd v dd s3 s4 a1 adg1204 pin 1 indicator nc = no connect 1v ss 2 s1 3 s2 9gnd 8v dd 7s3 4 d 5 n c 6 s 4 1 2 e n 1 1 a 0 1 0 a 1 top view (not to scale) adg1204 04779-003 notes 9 8 nc nc 04779-002 figure 2. tssop pin configuration 1. exposed pad tied to substrate, v ss . figure 3. lfcsp_vq pin configuration table 4. pin function descriptions pin no. mnemonic description tssop lfcsp_vq 1 11 a0 logic control input. 2 12 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. 4 2 s1 source terminal. can be an input or an output. 5 3 s2 source terminal. can be an input or an output. 6 4 d drain terminal. can be an input or an output. 7 to 9 5 nc no connection. 10 6 s4 source terminal. can be an input or an output. 11 7 s3 source terminal. can be an input or an output. 12 8 v dd most positive power supply potential. 13 9 gnd ground (0 v) reference. 14 10 a1 logic control input. truth table table 5. en a1 a0 s1 s2 s3 s4 0 x x off off off off 1 0 0 on off off off 1 0 1 off on off off 1 1 0 off off on off 1 1 1 off off off on
adg1204 rev. b | page 9 of 16 typical performance characteristics source or drain voltage (v) on resistance ( ? ) 200 180 160 140 120 100 60 80 0 20 40 ?18 ?15 ?12 ?9 ?6 ?3 3 9 15 0612 04779-010 18 t a = +25c v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v v dd = +13.5v v ss = ?13.5v figure 4. on resistance as a function of v d (v s ), dual supply source or drain voltage (v) on resistance ( ? ) 450 400 350 300 250 150 200 0 50 100 ?5 ?4 ?3 ?2 ?1 2 4 01 3 5 04779-004 v dd = +5.5v v ss = ?5.5v t a = +25c figure 5. on resistance as a function of v d (v s ), dual supply v dd = 13.2v v ss = 0v source or drain voltage (v) on resistance ( ? ) 450 400 350 300 250 150 200 0 50 100 024 6810121 04779-005 4 v dd = 12v v ss = 0v v dd = 10.8v v ss = 0v t a = 25c figure 6. on resistance as a function of v d (v s ), single supply source or drain voltage (v) on resistance ( ? ) 250 150 200 0 50 100 ?15 ?10 ?5 0 5 10 15 04779-006 v dd = +15v v ss = ?15v t a = +125c t a = +25c t a = +85c t a = ?40c figure 7. on resistance as a function of v d (v s ) for different temperatures, dual supply source or drain voltage (v) on resistance ( ? ) 600 400 500 300 200 0 100 0246810 04779-007 12 v dd = +12v v ss = 0v t a = +125c t a = +25c t a = +85c t a = ?40c figure 8. on resistance as a function of v d (v s ) for different temperatures, single supply temperature (c) leakage (na) 0.30 0.20 0.25 0.15 0.10 0.05 0 ?0.05 ?0.10 20 0 40 60 80 100 120 04779-008 i s (off) i d (off) i d , i s (on) v dd = +16.5v v ss = ?16.5v v bias = +10v/?10v figure 9. leakage currents as a function of temperature, dual supply
adg1204 rev. b | page 10 of 16 temperature (c) leakage (na) 0.20 0.15 0.10 0.05 0 ?0.15 ?0.10 ?0.05 ?0.20 20 0 40 60 80 100 120 04779-009 i s (off) i d (off) i d , i s (on) v dd = 13.2v v ss = 0v v bias = 10v/1v figure 10. leakage currents as a function of temperature, single supply logic, in x (v) i dd (a) 60 50 40 30 10 20 0 02468101214 04779-011 v dd = +12v, v ss = 0v v dd = +15v, v ss = ?15v i dd per channel t a = +25c figure 11. i dd vs. logic level v s (v) charge injection (pc) 6 4 2 0 ?4 ?2 ?6 ?15 ?10 ?5 0 5 10 15 04779-014 v dd = +12v, v ss = 0v v dd = +5v, v ss = ?5v v dd = +15v, v ss = ?15v source to drain drain to source t a = +25c figure 12. charge injection vs. source voltage temperature (c) time (ns) 250 200 150 100 50 0 ?40 ?20 40 20 06 0 8 0 1 0 0 04779-015 1 2 0 v dd = +12v, v ss = 0v v dd = +15v, v ss = ?15v figure 13. transition times vs. temperature frequency (hz) off isolation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 100k 1m 10m 100m 1g 04779-016 v dd = +15v v ss = ?15v t a = +25c figure 14. off isolation vs. frequency frequency (hz) crosstalk (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 10k 100k 1m 10m 100m 1g 04779-017 v dd = +15v v ss = ?15v t a = +25c s1 to s2 s2 to s4 figure 15. crosstalk vs. frequency
adg1204 rev. b | page 11 of 16 frequency (hz) on response (db) 0 ?10 ?5 ?15 ?25 ?20 ?30 10k 100k 1m 10m 1g 100m 10g 04779-018 v dd = +15v v ss = ?15v t a = +25c figure 16. on response vs. frequency frequency (hz) thd + n (%) 10.00 1.00 0.10 0.01 10 100 1k 10k 100k 04779-019 load = +10k ? t a = +25c v dd = +5v, v ss = ?5v, v s = +3.5vrms v dd = +15v, v ss = ?15v, v s = +5vrms figure 17. thd + n vs. frequency v bias (v) capacitance (pf) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 04779-031 s2 s3 s1 s4 d v dd = +15v v ss = ?15v t a = +25c figure 18. off capacitance vs. source voltage v bias (v) capacitance (pf) 6.5 6.1 6.3 5.9 5.7 5.5 5.3 5.1 4.9 4.7 4.5 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 04779-032 s2 s3 s1 s4 v dd = +15v v ss = ?15v t a = +25c figure 19. on capacitance vs. source voltage v bias (v) capacitance (pf) 9 7 8 5 6 4 3 2 1 0 2 04 68 1 0 04779-033 1 2 source/drain on source off drain off v dd = 12v v ss = 0v t a = 25c figure 20. capacitance vs. source voltage, single supply
adg1204 rev. b | page 12 of 16 test circuits i ds sd v s 04779-020 v sd v s a a v d i s (off) i d (off) 04779-021 sd a v d i d (on) nc nc = no connect 04779-022 figure 21. on resistance figure 22. off leakage figure 23. on leakage v s s1 d gnd c l 35pf r l 300? v out 50% 50% 90% 90% address drive (v in ) ) v out a0 a1 s4 s3 s2 v s1 v s4 en 2.4v 0v 3v t transition t transition v dd 0.1f v ss v dd v ss 0.1f 04779-023 figure 24. address to output switching times address drive (v in ) v out v s s1 d gnd c l 35pf r l 300 ? 50? v out a0 a1 s4 s3 s2 v s1 en 2.4v v dd 0.1f v ss v dd v ss 0.1f 04779-024 t bbm 80% 80% 0v 3v figure 25. break-before-make time delay enable drive (v in ) s1 d gnd c l 35pf r l 300 ? v out a0 a1 s4 s3 s2 v s en v dd 0.1f v ss v dd v ss 0.1f v s 50? 04779-025 t off (en) t on (en) 50% 50% 0.9v o 0.9v o output 0v 3v v o 0v figure 26. enable-to-output switching delay
adg1204 rev. b | page 13 of 16 sd v s gnd r s sw off q inj = c l v out sw off sw on sw off sw off a2a1 en v dd v ss v dd decoder v ss v out v out v in v in v out c l 1nf 04779-026 sw on figure 27. charge injection v out 50? network analyzer r l 50? s d 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 04779-027 figure 28. off isolation v out 50? network analyzer r l 50 ? s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 04779-028 figure 29. bandwidth channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 04779-029 figure 30. channel-to-channel crosstalk v out r s audio precision r l 10k? in v in s d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 04779-030 figure 31. thd + noise
adg1204 rev. b | page 14 of 16 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between d and s. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, which is measured with reference to ground. c d (off) the off switch drain capacitance, which is measured with reference to ground. c d , c s (on) the on switch capacitance, measured with reference to ground. c in the digital input capacitance. t on (en) the delay between applying the digital control input and the output switching on. t off (en) the delay between applying the digital control input and the output switching off. t trans the delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by ?3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental.
adg1204 rev. b | page 15 of 16 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 32. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters * compliant to jedec standards mo-220-veed-1 except for exposed pad dimension. * 1.45 1.30 sq 1.15 050808-b 1 0.50 bsc 0.75 0.60 0.50 0.25 min top view 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 12 4 10 6 7 9 3 coplanarity 0.08 exposed pad (bottom view) s eating plane 3.15 3.00 sq 2.85 2.95 2.75 sq 2.55 pin 1 indicator 0.60 max 0.60 max pin 1 indicator figure 33. 12-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-12-1) dimensions shown in millimeters ordering guide model temperature range packag e description package option adg1204yruz 1 ?40c to +125c 14-lead thin shrink small outline package (tssop) ru-14 adg1204yruz-reel 1 ?40c to +125c 14-lead thin shrink small outline package (tssop) ru-14 adg1204yruz-reel7 1 ?40c to +125c 14-lead thin shrink small outline package (tssop) ru-14 adg1204ycpz-500rl7 1 ?40c to +125c 12-lead lead frame chip scale package (lfcsp_vq) cp-12-1 adg1204ycpz-reel7 1 ?40c to +125c 12-lead lead frame chip scale package (lfcsp_vq) cp-12-1 1 z = rohs compliant part..
adg1204 rev. b | page 16 of 16 notes ?2005C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04779-0-2/09(b)

▲Up To Search▲

Price & Availability of ADG120409

	To Download ADG120409 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .